Referring to FIG. 1A, a floating gate memory cell 105 according to the conventional art is shown. As depicted in FIG. 1A, the cell 105 is fabricated about a semiconductor substrate 110. The cell 105 comprises a source region 115 and a drain region 120. A channel region 125 is disposed between the source 115 and drain 120. A floating gate 130 is formed above the channel region 125. A first isolating layer 135 is disposed between the floating gate 130 and the channel region 125. A control gate 140 is formed above the floating gate 130. A second isolating layer 145 is disposed between the control gate 140 and the floating gate 130.
In a p-channel cell 105, the substrate 110 is p-type semiconductor. The source 115 and drain 120 regions are formed by doping the substrate 110 with an impurity, wherein heavily n-doped semiconductor. The channel region 125 is the portion of the p-type substrate 110 located between the n-type source 1115 and drain 120. The floating gate 130 and the control gate 140 are typically polysilicon layers. The first 135 and second 145 insulating layers are typically a dielectric.
The floating gate 130 provides a charge-trapping region utilized for storing a bit of data. The presence of charge on the floating gate 130 acts to block a high signal (e.g., 5V) present on the control gate 140 such that a conducting channel 125 is not induced between the source 115 and drain 120. When there is no charge stored on the floating gate 130, the high signal (e.g., 5V) present on the control gate 140 induces a conducting channel 125 between the source 115 and drain 120. Hence, the state of a bit is determined by the presence or absence of current flowing between the source 115 and drain 120 as a result of a first signal (e.g., 5V) applied to the control gate 140 and a second signal (e.g., 1V) applied to the drain 115.
Typically, reading a cell 105 entails applying a positive voltage (e.g., 5V) to the control gate 140, and a positive voltage (e.g., 1V) to the drain region 120. The source region 115 and substrate 110 are grounded. If a large current flows from the drain 120 to the source 115 across the channel region 125, the state of the cell represents a “1” bit. If substantially no current flows from the drain 120 to the source 115, the state of the cell represents a ‘0’ bit.
Erasing the memory cell 105, in one configuration, entails applying a positive voltage (e.g., 5V) to the source region 115, a negative voltage (e.g., −10V) to the control gate 140, and tri-stating (e.g., high impedance) the drain region 120. The large potential difference between the control gate (−10V) 140 and the source (5V) 115 causes electrons trapped on the floating gate 130 to be repelled by the control gate 140 and attracted by the source 115. The electrons tunnel from the control gate 130 through the first insulating layer 135 to the source 115.
In another configuration, erasing the memory cell 105 entails applying a large positive voltage (e.g., 10V) to the source region 115, grounding the control gate 140, and tri-stating (e.g., high impedance) the drain region 120. The large potential difference between the control gate (10V) 140 and the source (10V) 115 causes electrons trapped on the floating gate 130 to be attracted by the source 115. The electrons tunnel from the control gate 130 through the first insulating layer 135 to the source 115.
Programming the cell 105 entails applying a positive voltage (e.g., 8.5V) to the control gate 140, a positive voltage (e.g., 5V) to the drain 120, while grounding the source 115 and substrate 110. The potential difference between drain 120 and source 115, causes electrons to flow across the channel from the source (0V) 115 toward the drain (5V) 120. The high voltage applied to the control gate 140 causes some electrons to overcome the potential barrier of the first insulating layer 135. Thus, electrons are injected into the floating gate 130.
Referring now to FIG. 1B, another floating gate memory cell 155 according to the conventional art is shown. In the depicted n-channel cell 155, the substrate 160 is n-type semiconductor, the source 165 and drain 170 regions are formed by doping the substrate 160 with an impurity, wherein heavily p-doped semiconductor is formed. The channel region 175 is the portion of the n-type substrate 160 located between the p-type source 165 and drain 170. The floating gate 180 and the control gate 190 are typically polysilicon layers. The first 185 and second 195 insulating layers are typically a dielectric.
Typically, reading a cell 155 entails applying a low voltage (e.g., 5V) to the control gate 190, and a small voltage (e.g., 1V) to the source region 165, while grounding the drain region 170. If current flows from the source 165 to the drain 170 across the channel region 175, the state of the cell represents a ‘0’ bit. If substantially no current flows from the source 165 to the drain 170, the state of the cell represents a ‘1’ bit.
Erasing the memory cell 155 entails applying a negative voltage (e.g., −20V) to the control gate 190, grounding (e.g., 0V) the source region 165, and tri-stating (e.g., high impedance) the drain region 170. The large potential difference between the control gate (−20V) 190 and the source (0V) 165, causes electrons trapped on the floating gate 180 to be attracted by the source gate 165. Thus, electrons tunnel through the potential barrier of the first insulating layer 185 and are collected by the source 165.
Programming the cell 155 entails grounding (e.g., 0V) the control gate 190, applying a negative voltage (e.g., −20V) to the source 165, while tri-stating (e.g., high impedance) the drain 170. The large potential difference between control gate (0V) 190 and source (−20V) 165, causes electrons to be attracted by the control gate 190. Thus, electrons tunnel through the potential barrier of the first insulating layer 185 and are trapped by the floating gate 180.
Referring now to FIG. 2, a flash memory array 205 according to the conventional art is shown. As depicted in FIG. 2, the memory array 205 comprises a plurality of floating gate memory cells 210 arranged in columns and rows. Each cell 210 comprises a floating gate, a control gate, a drain, and a source.
For p-channel cells 210, the control gate of each cell 210 in a row is coupled to one of N corresponding wordlines (W1, W2, W3, . . . WN). The drain of each cell 210 in a column is coupled to one of M bitlines (B1, B2, B3, . . . BM). The source of each cell 210 is typically coupled in common with each other. Alternatively, the sources are coupled in common with each other for block, sectors, or other subdivisions of the entire array. In yet another configurations, the source of each cell in a column is coupled to one of M sub-bitlines.
For an n-channel cells 210, the control gate of each cell 210 in a row is coupled to one of N corresponding wordlines (W1, W2, W3, . . . . WN). The source of each cell 210 in a column is coupled to one of M bitlines (B1, B2, B3, . . . BM). The drain of each cell 210 is typically coupled in common with each other.
During programming of a p-channel cell connected to a particular bitline (e.g., B2), a positive voltage is also applied to the drain of each non-selected cell attached to the same bitline (e.g., B2). The non-selected cell does not have an induced n-channel between the source and drain, because the gate is grounded by the respective non-selected wordline (e.g., W1). However, despite the lack of an induced n-channel, a leakage current will flow from the source to the drain. For channel lengths of 2 micrometers or less, the leakage current is known to increase by 2-3 orders of magnitude for each 0.1 micrometer decrease in channel length for a given drain to source voltage (VDS).
The increased leakage current from each non-selected cell connected to the particular wordline is problematic. A typically bit line will have N (e.g., 512 or more) cells connected to it. Therefore, the total current on the bit line will be:IT=IP+(N−1)−IL Where IT is the total current, IP is the current to be supplied to the cell being programmed, N−1 is the number of non-selected cells attached to the bitline, and IL is the leakage current in each non-programmed cell. The increased total current flowing on a bitline will result in a potential drop in the bitline programming voltage, due to the finite resistance of typical bitlines. Furthermore, as the total current increases due to increased leakage current of non-selected cells, the power supply circuit on the flash memory device must be increased (e.g., occupy more area on the chip) or an additional off chip supply must be provided.
Hence, short channel floating gates suffer increasing leakage current as the device is scaled. As a result, flash memory devices suffer from increasing voltage drop on the bitlines, and the need for a larger power supply or an extra off chip power supply.